製品情報

ISP1016E-80LT44

型番：ISP1016E-80LT44
ブランド：Lattice

日付：13+RoHS
パッケージ：QFP
原価：65
数量：59840
PDF電子ファイル：

注文電話：86755-83294757
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注釈：Brand new in stock专业分销Lattice

詳細な説明

ISP1016E - High-Density Programmable Logic - Lattice Semiconductor

Features

• HIGH-DENSITY PROGRAMMABLE LOGIC

— 2000 PLD Gates

— 32 I/O Pins, Four Dedicated Inputs

— 96 Registers

— High-Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

• HIGH-PERFORMANCE E2

CMOS®

TECHNOLOGY

— fmax = 125 MHz Maximum Operating Frequency

— tpd = 7.5 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

• ispLSI OFFERS THE FOLLOWING ADDED FEATURES

— In-System Programmable™ (ISP™) 5-Volt Only

— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality

— Reprogram Soldered Device for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

Minimize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• pLSI/ispLSI DEVELOPMENT TOOLS

pDS®

Software

— Easy to Use PC Windows™ Interface

— Boolean Logic Compiler

— Manual Partitioning

— Automatic Place and Route

— Static Timing Table

ispDS+™ Software

— Industry Standard, Third-Party Design

Environments

— Schematic Capture, State Machine, HDL

— Automatic Partitioning and Place and Route

— Comprehensive Logic and Timing

**注意 & Noted:

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