製品情報

ISPLSI5128VE100LT128-80I

型番：ISPLSI5128VE100LT128-80I
ブランド：Lattice

日付：13+
パッケージ：QFP128
原価：100
数量：5840
PDF電子ファイル：

注文電話：86755-83294757
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注釈：Brand new in stock专业分销Lattice

詳細な説明

ISPLSI5128VE100LT128-80I

In-System Programmable 3.3V SuperWIDE High Density PLD

Features

Second Generation SuperWIDE HIGH DENSITY

IN-SYSTEM PROGRAMMABLE LOGIC DEVICE

3.3V Power Supply

User Selectable 3.3V/2.5V I/O

6000 PLD Gates / 128 Macrocells

96 I/O Pins Available

128 Registers

High-Speed Global Interconnect

SuperWIDE Generic Logic Block (32 Macrocells) for

Optimum Performance

SuperWIDE Input Gating (68 Inputs) for Fast

Counters, State Machines, Address Decoders, etc.

Interfaces with Standard 5V TTL Devices

HIGH PERFORMANCE E2

CMOS®

TECHNOLOGY

fmax = 180 MHz Maximum Operating Frequency

tpd = 5.0 ns Propagation Delay

TTL/3.3V/2.5V Compatible Input Thresholds and

Output Levels

Electrically Erasable and Reprogrammable

Non-Volatile

Programmable Speed/Power Logic Path Optimization

IN-SYSTEM PROGRAMMABLE

Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality

Reprogram Soldered Devices for Faster Debugging

100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND

3.3V IN-SYSTEM PROGRAMMABLE

ARCHITECTURE FEATURES

Enhanced Pin-Locking Architecture with SingleLevel Global Routing Pool and SuperWIDE GLBs

Wrap Around Product Term Sharing Array Supports

up to 35 Product Terms Per Macrocell

Macrocells Support Concurrent Combinatorial and

Registered Functions

Macrocell Registers Feature Multiple Control

Options Including Set, Reset and Clock Enable

Four Dedicated Clock Input Pins Plus Macrocell

Product Term Clocks

Programmable I/O Supports Programmable Bus

Hold, Pull-up, Open Drain and Slew Rate Options

Four Global Product Term Output Enables, Two

Global OE Pins and One Product Term OE per

Macrocell

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